This invention relates to programmable logic array integrated circuits, and more particularly to programmable logic array integrated circuits with improved arrangements of the programmable logic elements and improved interconnections between those elements. The invention also relates to the provision of relatively large blocks of random access memory ("RAM") on programmable logic array integrated circuit devices. This invention still further relates to logic devices employing look up tables, and more particularly to improved ways of providing fast carry functions in such devices when the devices are to be used for such purposes as performing addition, subtraction, and counting.
Programmable logic arrays are known in which substantial numbers of relatively elementary individual programmable logic elements are provided in a two-dimensional array. The array also includes a grid of intersecting signal conductors for conducting logic signals to, from, and between the programmable logic elements. Such programmable logic arrays are shown, for example, in Carter U.S. Pat. Nos. 4,642,487, 4,706,216, and 4,758,985, and in Freeman U.S. Pat. No. 4,870,302.
As integrated circuit fabrication techniques progress, it becomes possible to put more and more programmable logic elements on a chip. As the number of elements increases, it becomes important to improve the techniques used to interconnect them. For example, it is important to provide enough interconnection pathways between the programmable logic elements so that the capabilities of those elements can be fully utilized and so that complex logic functions (requiring concatenation of programmable logic elements) can be performed, without providing so many such pathways that there is a wasteful excess of this type of resource. Similarly, as the number of programmable elements increases, the complexity of the logic which can be performed also increases. But this in turn tends to increase the complexity of the task of programming the circuit unless additional logical structure is included in the circuit to help correspondingly structure the programming task.
There is always room for further improvement, however, and there are some situations in which the provision of additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuit and programming complexity. Such additional interconnection paths may be desirable for making frequently needed kinds of interconnections, for speeding certain kinds of interconnections, for allowing short distance connections to be made without tying up more general purpose and therefore long distance interconnection resources, etc. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
It is therefore an object of this invention to provide improved programmable logic array integrated circuits.
It is a more particular object of this invention to provide programmable logic array integrated circuits with additional possibilities for interconnections between the logic modules.
It is a further object of this invention to provide improved techniques for organizing and interconnecting the programmable logic elements in programmable logic array integrated circuits.
Cliff et al. U.S. Pat. Nos. 5,550,782 and 5,689,195 show programmable logic array integrated circuit devices with relatively large blocks of random access memory ("RAM") in addition to the usual large number of programmable logic modules and the usual programmable network of interconnection conductors. (These two references are hereby incorporated by reference herein.) These RAM blocks can be programmed at the same time that the rest of the device is programmed and thereafter used as read-only memory ("ROM") to perform logic, arithmetic functions, state machine operations, etc., that may be more efficiently performed in one large memory block (or a small number of such blocks) rather than in several of the individually relatively small logic modules. Alternatively, the RAM blocks may be used as random access memory during use of the device to perform logic.
From the foregoing it will be seen that the above-mentioned RAM blocks have several possible uses and require several different modes of operation. They should be programmable like other memory cells on the device (i.e., the other memory cells that control the functioning of the logic modules and the interconnection conductor network). This is necessary when the RAM blocks are to be used as ROM. Their programming in this way should be capable of verification like other memory cells on the device (i.e., reading out of the programmed data to ensure that the memory cells are programming properly). The RAM blocks should also be programmable as random access memory during use of the device to perform logic. And the RAM blocks should be readable as random access memory or read-only memory, also during use of the device to perform logic. All of these possible uses and modes of operation of these RAM blocks tend to significantly complicate the circuitry required to provide such blocks.
In view of the foregoing, it is still another object of this invention to improve and simplify the provision of blocks of RAM on programmable logic array integrated circuit devices.
It is a more particular object of this invention to provide RAM block circuitry for use on programmable logic array integrated circuit devices that facilitates programming and verification of the RAM block for use as ROM, and that also facilitates programming and reading the block as RAM during use of the device to perform logic.
Programmable logic devices are also known in which programmable look up tables are used to perform relatively elementary logic functions (see, for example, Wahlstrom U.S. Pat. No. 3,473,160 (FIG. 8) and Pedersen et al. U.S. Pat. No. 5,260,610). A look up table may provide as an output any desired logical function of several inputs. The outputs of several such look up tables may be combined (e.g., by other similar look up tables) in any desired way to perform much more complex logic functions.
Look up tables which are a good size for performing many elementary logic functions in programmable logic devices tend to be too large for performing the extremely simple functions required to provide two-input adders (including subtracters) and various kinds of counters. For example, four-input look up tables are a very good size for general use, but are larger than necessary for use in the individual binary places of adders and counters. Nevertheless, adders and counters are very often required in digital logic. It is therefore wasteful to use four-input look up tables for adders and counters. This is especially so when fast carry logic is used because for each binary place one four-input look up table is required to provide the sum out bit, and another four-input look table is required to provide the carry out bit. Neither of these look up tables is being fully utilized. Moreover, if large numbers of bit positions or places are required, the need to use two look up tables per bit position may exact a significant speed penalty because of the extensive use which must be made of the interconnect circuitry to interconnect the large number of look up tables involved.
In view of the foregoing, it is an object of this invention to provide improved ways of implementing adders (including subtracters) and counters in programmable logic devices made up of programmable look up tables.
It is a more particular object of this invention to provide programmable logic devices made up of look up tables in which adders and counters can be implemented more efficiently and with less waste of look up table resources.
It is still another more particular object of this invention to provide ways of achieving faster adders and counters in programmable logic devices made up of look up tables.